The present invention relates to a method and apparatus for addressing a random access memory.
In a typical radar system generally referred to at 15 such as shown in FIG. 1, a radar transmitter 16 transmits trains of pulses to an antenna 17. The antenna 17, which may scan either incrementally or continually, aims each train of pulses in a specific direction successively. Each specific direction or aim of the antenna 17 is commonly termed a "look". Thus, a train or series of a predetermined number of pulses is transmitted for each radar "look". The reflected transmitted pulses for each "look" are sensed by the antenna, and amplified by a receiver 18. The first signal received for each "look" is reflected from the target closest to the radar antenna 17, while the later pulses are reflected from targets farthest from the antenna 17. Each amplified reflected signal is converted to a digital number which corresponds to the amplitude or other characteristic of the pulse which is indicative of a target or a lack thereof. For each reflected pulse, the receiver generates a sequence of numbers corresponding to the number of ranges of distance for a particular radar application. Each one of these numbers or data items is termed a "range gate". Thus, when a pulse is transmitted, the numbers are generated for adjacent range gates for such pulse prior to the generation of each succeeding pulse. Thus, for the first pulse of each series, the strength of the reflected pulse at a particular time may indicate a target for any one of the range gates. These data items are input to a memory apparatus 20, to a signal processor 21 and then to a display or control unit 22 for indication of targets or other uses where it is desired to know the presence and distance of a target from the antenna 17 for each "look", for example.
If a target could be detected accurately with one transmitted pulse for each "look", it is apparent that the signal processor 21 could receive each sequence of data items corresponding to range gates, and determine the distance of the target from the radar. However, for accurate detection it is necessary to transmit a series of pulses for each "look". Therefore, the receiver 18 outputs each sequence of range gate data numbers after the transmission of each pulse of the series in sequence. In other words, target information for the various range gates is output by the receiver for the first pulse of a "look" which is followed by the range gate information for the second pulse of the same "look", and finally the range gate information for the final pulse of the "look" is output. However, in order to properly process the range gate information for the pulses of each radar look, it is necessary that the signal processor 21 receives the data items for each range gate in succession for all of the radar pulses transmitted during a particular look. In other words, the signal processor 21 should receive in sequence, data items relating to a first range gate for all of the pulses of a particular look, then data items relating to a second range gate for all of the pulses of such look, and finally the data items for the final range gate for all of such radar pulses of such look.
Assume, for example, and for the sake of simplicity of explanation, that a series of five radar pulses are transmitted for each antenna "look" and that there are three range gates for each radar pulse, then the memory apparatus 20 receives and transmits 15 data items for each "look". If the 5 pulses of each "look" are designated 0, 1, 2, 3, and 4; and each range gate is designated as A, B, and C, the 15 data items are received by the memory apparatus 20 in the following sequence: 0A, OB, OC, 1A, 1B, 1C, 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B, and 4C. However, to properly process such information, the signal processor 21 should receive such data items for all of the pulses of the look for each range bin in sequence; that is, the sequence of inputs to the signal processor should be 0A, 1A, 2A, 3A, 4A, 0B, 1B, 2B, 3B, 4B, 0C, 1C, 2C, 3C, and 4C. In this latter output sequence from the memory apparatus 20, the signal processor 21 receives the results of all 5 pulses from the range inteval or gate A, then all 5 pulses from the ranges interval, B, and all 5 pulses from the range interval C. The memory apparatus 20 rearranges such data items; and is typically termed a corner turn buffer or memory.
The problem of rearranging and reading out such data items is relatively simple provided that the data of the corner turn memory apparatus can be read out completely for on "look" prior to the writing in of the data for the next "look". However, since radar systems are continually transmitting and receiving reflected pulses, there is insufficient time for such complete read-outs to occur before the next write-in. Heretofore, in radar applications, it was necessary to utilize what is termed a double buffer corner turn memory apparatus, which utilizes two separate memory arrays. While the data is being written into the first buffer in one sequence, it is being read out of the second buffer in the proper sequence. Then the buffers are switched so that the data items are being read out of the first buffer while new data items are being written into the second buffer. Such an arrangement, although satisfactory, requires double the amount of memory hardware required. Heretofore, attempts to utilize a single buffer or memory apparatus such as referred to at 23 that is structured to read out the data items from one radar "look" simultaneously with the writing in of the data items from the next "look" resulted in a complicated addressing arrangement or circuitry that required more apparatus than the conventional double buffered corner turn memory.
Therefore, it is desirable to provide an improved single corner turn buffer 23 as shown in FIG. 1 and method suitable for radar applications that has the necessary speed of operation corresponding to the double buffer corner turn memory while utilizing a relatively simple method and address circuitry 24 therefor.